In this paper, an all-digital foreground calibration algorithm is proposed to mitigate harmonic distortions in open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converters (ADCs). By calculating the 3rd-order nonlinearity coefficients of the VCO-based ADC digital output, a look-up table is established to achieve nonlinearity calibration. A 40 MHz-bandwidth VCO-based ADC with 5 bit quantization and a clock frequency of 1.6 GHz was designed and simulated in 40 nm CMOS GP process, while the proposed calibration algorithm is implemented in a FPGA board. The experimental results show that the ADC signal-to-noise-distortion ratio (SNDR) is improved from 40.8 dB to 56.4 dB, and the ADC signal-to-noise ratio (SNR) is 58.9 dB, with limited hardware resources and only 104 clock cycles to converge.