In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure. Optimization of the device is done for low power applications. Heterojunction engineering is done to optimize the position of the Si:SiGe junction. Subsequently, band gap engineering is incorporated using variations in doping, gate work function, the mole fraction of SiGe and the dielectric constant. Comparison of the optimized, heterostructured silicon channel using numerical simulations indicates that I_ON increases from 0.12 to 15 μA μm⁻¹, I_ON/I_OFF increases from 4 × 10⁶ to 3 × 10⁹, and the subthreshold slope decreases from 80 to 43 mV dec⁻¹ for a 22 nm channel with a supply voltage of 0.7 V.