Cathode shorts are an essential part in light-triggered thyristors (LTTs) that are utilized to achieve adequate dv/dt capability and switching characteristics. In this paper, we designed cathode shorts structures specifically for small-size LTTs; the patterns and structural parameters were shown. Devices were fabricated and measured, and the influences of the cathode shorts on device performance were examined. The results showed that, based on the optimized design, the cathode shorts allowed excellent dv/dt capability and switching performance while achieving good optoelectronic properties.

Recent work showing a strong quality improvement of the Si/SiO2 material system by low temperature atomic hydrogen annealing (AHA), and the fact that III–V semiconductors outperform Si in many applications makes the investigation of AHA on III–V/high-k interfaces to a very interesting topic. In this work, the potential of AHA as a low temperature annealing treatment of InGaAs metal–oxide–semiconductor field-effect transistors is presented and compared to conventional annealing in a rapid thermal process (RTP) system using forming gas. It is found that post metal annealing in atomic hydrogen greatly enhances the quality of the metal–oxide–semiconductor structure in terms of effective mobility, minimum subthreshold swing, and reliability. The device performance is comparable to RTP annealing but can be performed at a lower temperature, which opens up for integration of more temperature-sensitive materials in the device stack.

Improvement of endurance characteristics has been a hot area of phase-change memoryresearch. The properties of a phase-change material are believed to play an important role in device endurance. Repeated SET–RESET operation always leads to material failure problems, such as composition deviation and phase separation. Moreover, the quality of the electrode and the electrode contact also determine the endurance characteristics. In this study, C nanolayers were periodically inserted into the phase-change material Ge2Sb2Te5 (GST) to fabricate a superlattice-like (SLL) structure. Although some of C bonded with some of the Ge, Sb and Te atoms, more C atoms prefer nanometer-scale clusters at the grain boundary in the SLL film. The typical local configuration of GST was unchanged when artificial C nanolayers were inserted. Transmission electron microscopy experiments revealed that the bonded C atoms and nanometer-scale C clusters may occupy the spontaneously created holes and defects, preventing composition deviation of the phase-change material and prolonging the electrode service life. The contact surface between the phase-change material and the electrode is also improved. As a result, we found that the endurance cycle could be improved by up to 106 for a GST/C SLL film-based device.

The local integration of III–Vs on Si is relevant for a wide range of applications in electronics and photonics, since it combines a mature and established materials platform with desired physical properties such as a direct and tuneable bandgap and high mobility. The large thermal expansion coefficient and lattice mismatch, however, pose a challenge for the direct growth of III–Vs on Si. In this paper we will review fabrication concepts to overcome this mismatch for the local integration of III–Vs on Si. In particular, we will briefly discuss processing methods based on aspect ratio trapping, nanowire growth, and template-assisted selective epitaxy (TASE). The focus of this review will be on the latter, where we will provide an overview of the different possibilities and embodiments of TASE and their promise for locally integrated active photonic devices.

DC-pulse magnetron sputtering was utilized to deposit a 300 nm-thick n-type GaN thin film that was co-doped with Si–Sn onto an amorphous glass substrate with a ZnO buffer layer. The deposited thin films were then subjected to post-growth thermal annealing at temperatures of 300 °C, 400 °C, or 500 °C to enhance their crystal quality. Hall measurements revealed that the film annealed at 500 °C had the lowest thin-film resistance of 0.82 Ω cm and the highest carrier concentration of 3.84 × 1019 cm−3. The thin film surface was studied using atomic force microscopy; the film annealed at 500 °C had an average grain size and surface roughness of 25.3 and 2.37 nm, respectively. Furthermore, the x-ray diffraction measurements revealed a preferential (002) crystal orientation and hexagonal wurtzite crystal structure at 2θ ≈ 34.5°. The thin film had a full width at half maximum value of 0.387°, it was also found to be very narrow. Compositional analysis of the films was conducted with x-ray photoelectron spectroscopy and verified that both Si and Sn were doped into the GaN film utilizing covalent bonding with N atoms. Finally, the film annealed at 500 °C had a high optical transmittance of 82.9% at 400–800 nm, a high figure of merit factor of 490.3 × 10−3 Ω−1, and low contact resistance of 567 Ω; these excellent optoelectronic properties were attributed to the film’s high electron concentration and indicate that the material is feasible for application in transparent optoelectronic devices.

In this work, graphene oxide (GO)/TiO2 heterostructures for resistive random access memory devices were fabricated, and the composition and microstructure of TiO2 and GO were characterized by x-ray diffraction, Raman spectroscopy, scanning electronic microscopy, and transmission electron microscopy. The resistive characteristics of the fabricated devices were investigated, and the remarkable improvement in cycle-to-cycle uniformity and high ON/OFF ratio of the TiO2 thin film-based memory device were realized by introducing a thin GO layer. The formation/rupture of the conductive filament through the migration of oxygen vacancies in the TiO2 substrate was responsible for the resistive switching. Owing to the different activation energies of reduction and oxidation of the GO, the set voltage became larger than the reset voltage. According to the linear fitting of double logarithm I–V plots, the conduction mechanism in low and high resistance states was governed by the ohmic mechanism and trap-controlled space charge limited current, respectively. The oxygen migration-induced oxidation/reduction in GO rendered it a good oxygen vacancy reservoir, which is responsible for the enhanced cycle-to-cycle uniformity and high ON/OFF ratio.

In this study, the effect of barrier thickness on the DC and RF performances of AlGaN/GaN high-electron mobility transistors (HEMTs) on silicon for millimeter wave applications is experimentally investigated. GaN HEMT devices with different barrier thicknesses were fabricated and characterized. While the device with the thinnest barrier exhibited the highest extrinsic transconductance (gm) resulting from the shortest gate-to-channel distance, such configuration suffered from the lowest unit current-gain cut-off frequency (fT) due to the increase of the total gate capacitance. Moreover, degradation in the output power was observed for devices with thinner barriers. Such degradation was related to the severe knee walkout as evidenced from drain-lag characterization.

The development of nanoporous gallium nitride (NP-GaN) has widened the material properties and applications in third-generation semiconductor areas. NP-GaN has been used in laser emitters, light-emitting diodes, optical sensors, and optical energy storage devices. In this paper, we reviewed the most recent progress in the NP-GaN field by electrochemical etching. The etched GaN has many superior properties compared with original GaN templates, such as stronger photoluminescence intensity, thermal conductivity, piezo-electricity, more accessible area, stress relief, and refractive index. These advantages will make GaN more widely used in the field of optics and optoelectronics. Pore formation can be controlled by adjusting the applied potential and etching time. The NP-GaN makes the material of GaN have broader application prospects. We introduced in detail the application prospects of different GaN based processes and subsequent application methods in optoelectronics, sensors, and materials themselves. This review will help to improve further development of NP-GaN applications.

In this paper, the undoped vertical dual-bilayer tunnel field effect transistor (UV-DBL-TFET) at a low operating voltage (0.5 V) is introduced, and its DC and RF performance parameters are compared with those of the conventional charge plasma-based symmetrical gate electron–hole bilayer TFET (CP-SG-EHBTFET). The charge plasma technique is used in the proposed device to induce the source/drain and electron–hole dual-bilayer channel dopants. Due to the dopingless architecture of the proposed UV-DBL-TFET, its fabrication is simple and efficient, and it does not require an expensive thermal annealing process. Due to its dopingless architecture, the proposed UV-DBL-TFET is immune against random dopant fluctuations. In the study, the quantum confinement effects in the TCAD simulation have been successfully modelled using the Schrodinger approach and the density gradient model. Compared to the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has a dual EHB channel, triggers dual line tunnelling, and doubles the band-to-band tunnelling rate and the ON current. Compared to the I ON of 47.33 μA μm−1 and AVSS of 13.53 of the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has almost double the ON current of 93.46 μA μm−1 with a reduced AVSS of 12.3 mV dec−1. The proposed UV-DBL-TFET also gives improved RF/analog performance. Compared to the transconductance (g m) of 0.337 mS, the cut-off frequency (f T) of 65.17 GHz, and the gain-bandwidth-product (GBW) of 16.5 GHz of the conventional CP-SG-EHBTFET, the proposed UV-DBL-TFET has a g m of 0.665 mS, a f T of 129.0 GHz, and an GBW of 32.6 GHz, an almost doubled improvement. Furthermore, the proposed UV-DBL-TFET-based CMOS inverter has also been comprehensively studied, and perfect complementary inverter action has been obtained, suggesting great potential for future low-power applications.

Heterostructures of two-dimensional layered materials, integrating two or more building blocks with complementing counterparts, can regulate the confinement and transportation of charge carriers via vacancy-induced defect and interfacial states. Herein, reduced graphene oxide-molybdenum disulfide (rGO-MoS2) nanohybrid were fabricated and reinforced with various polymers [poly methyl methacrylate (PMMA), poly (vinylidene fluoride) (PVDF), and PMMA-PVDF (20:80) blend] to study the resistive memory properties in a metal–insulator-metal configuration. The scanning electron microscopy analysis presents a hierarchical 3D flower-like MoS2 intercalated with rGO nanosheets. Transmission electron microscopy image exhibits MoS2 nanoflakes well interspersed and grafted on layered rGO sheets, forming sandwich heterostructures. Raman analysis shows a higher I D/I G ratio for rGO-MoS2 than rGO, demonstrating numerous defect states in rGO. The x-ray diffraction analysis of the polymer blend containing rGO-MoS2 exhibits β-crystal phases with a polarity-dependent internal electric field (E-field). The J-V characteristics of pure MoS2-polymer films display a write-once-read-many behavior with a current I ON/I OFF ratio of ∼102–103, in contrast to pristine polymer films exhibiting repeatable electrical hysteresis. Instead, the rGO-MoS2-based devices display bipolar characteristics (I ON/I OFF ratio of ∼103–104) due to charge transfer interaction with the conductive carbon substrates. The ferroelectric polarization-induced E-field coupled with the external bias is responsible for the improved memristive performances. A plausible conduction mechanism is proposed to discuss the carrier transport through the devices.

We have fabricated a device which includes two lateral p–n junctions on an n-type GaAs/Al0.33Ga0.67As heterostructure. A section of the n-type material has been converted to p-type by removing dopants and applying a voltage to a gate placed in this region. Controlled electroluminescence from both of the p–n junctions has been demonstrated by varying the applied bias voltages. An emission peak with a width of ∼8 nm is observed around 812 nm. The electroluminescence seen from both junctions is considered to originate from the GaAs quantum well layer in the device. The lithographic techniques that we have developed are compatible for further integration of gated quantum devices such as single-electron pumps to build on-demand single-photon sources.

Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified transfer length method (TLM) to obtain sheet resistances in the gated and ungated regions as well as to observe their gate electric field dependence. The modified TLM requires the contact resistance to be independent of the gate-source voltage, or changing current density. We verify this by performing measurements on conventional TLM structures in dark and UV conditions and observe a changing current density with constant contact resistance, enabling the development of the proposed method. The conventional and modified TLM give sheet resistances of 20.0 kΩ sq−1 ± 1.0 kΩ sq−1 and 27.5 kΩ sq−1 ± 0.8 kΩ sq−1, respectively. Using a traditional method for determining the channel resistance, the modified TLM improves the convergence of the channel resistances between the three devices, showing higher accuracy than the conventional TLM structures. Gate-source voltage dependence of the sheet resistances is seen in the ungated regions, leading to non-ideal behavior which cannot be observed using the traditional method and conventional TLM structures. These results and analysis methods are important in improving MOSFET parameter extraction and understanding the gate electric field effects on the channel and series resistances in β-Ga2O3 MOSFETs.

Silicon carbide (SiC) is a typical wide band-gap semiconductor material that exhibits excellent physical properties such as high electron saturated drift velocity, high breakdown field, etc. The SiC material contains many polytypes, among which 4H-SiC is almost the most popular polytype as it possesses a suitable band-gap and high electron saturated drift velocity. In order to produce 4H-SiC power devices with a high barrier voltage of over several thousand volts, the minority carrier lifetime of 4H-SiC single crystals must be carefully managed. In general, both bulk defects and surface defects in 4H-SiC can reduce the minority carrier lifetime. Nevertheless, as surface defects have received less attention in publications, this study reviews surface defects in 4H-SiC. These defects can be classified into a number of categories, such as triangle defect, pit, carrot, etc. This paper discusses each one individually followed by the introduction of industrially feasible methods to characterize them. Following this, the impact of surface defects on the minority carrier lifetime is analyzed and discussed. Finally, a particular emphasis is put on discussing various passivation schemes and their effects on the minority carrier lifetime of 4H-SiC single crystals. Overall, this review paper aims to help young researchers comprehend surface defects in 4H-SiC single crystal material.

We demonstrate area-selective doping of MoS2 field-effect transistors using 1,2-dichloroethane (DCE) solution. In the device manufacturing process, area-selective chemical doping was used to implement contact engineering in the source/drain region. X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy measurements were performed to confirm the blocked layer (BL) using a photoresist, which suppressed the doping effect of the DCE treatment. In the XPS results, the main core level of the MoS2 flake with BL did not shift, whereas that of the MoS2 flake without BL changed by approximately 0.24 eV. In the case of the MoS2 flakes with a BL, the vibrational modes of the Raman scattering did not shift. Conversely, the two Raman peaks of the MoS2 flake without BL red-shifted because of increasing electron–phonon scattering. The effect of area-selective doping was confirmed by electrical measurements. The field-effect mobility and the subthreshold swing were enhanced from 4.07 to 31.5 cm2 (V s)−1 and from 1.26 to 0.401 V/decade, respectively.

We introduce a novel superlattice structure for releasing GaN-based devices with selective photo-electrochemical (PEC) etching by incorporating a lattice-matched AlInN barrier in an InGaN/GaN sacrificial stack. A dopant-free two-dimensional hole gas is formed at the InGaN/AlInN interface due to the band bending and strong polarization discontinuity, which is revealed in simulations. PEC etching using the four period InGaN/AlInN superlattice exhibits almost three times higher etch rate and smoother etched surfaces when compared to conventional InGaN/GaN release layers. A systematic investigation with different AlInN layer thicknesses shows that a thin AlInN layer is able to achieve smooth surface with uniform etch process during the PEC while thicker AlInN exhibits poorer surface morphology although the etch rate was faster. Furthermore, it is found that using HNO3 as the electrolyte improved the etched surface smoothness compared to KOH when followed by a post-release HCl treatment. This structure will enable the release of high quality GaN layers and the fabrication of novel optical devices.

We report the temperature effects on the performance of ferroelectric field-effect transistor (FeFET)-based non-volatile memory (NVM) considering random grain phase variation in the ferroelectric layer through simulation. Based on the FE temperature effect model that accounts for both the transistor and ferroelectric degradation, we demonstrate that: (1) at a certain temperature, the memory window (MW) decreases with pronounced effect on low threshold voltage shift and its variation increases as the FE phase decreases; (2) with the temperature increases, the MW decreases with pronounced effect on high threshold voltage shift. The random grain phase variation further exacerbates the MW distribution, thus degrading the sensing margin. These results may provide insights for device design of high-performance FeFET-based NVMs.

We present a high-resolution electron tomography study of buried ultra-thin layers and their interfaces from the active region of a (Ga,In)As/(Al,In)As quantum cascade laser (QCL) test structure. Using a high-angle annular dark-field scanning transmission electron microscopy image series, a three-dimensional (3D) reconstruction of the complex layer structure is obtained. From this 3D information, we determine quantitative values for the chemical width and, simultaneously and independently, the root mean square roughness (rms) and lateral correlation length of the individual interfaces of a cascade using topographic height maps. The interfacial widths are comparably small for all interfaces within a cascade and the layer thicknesses show only a small standard deviation of less than one monolayer. The rms roughness is systematically lower at the direct (Ga,In)As-on-(Al,In)As interface compared to its inverse. In addition, using the one-dimensional height–height correlation function, different lateral correlation lengths along the two perpendicular ⟨011⟩ in-plane directions are detected indicating a distinct anisotropy of the interface morphology. Our accurate and comprehensive results on the QCL test structure will serve as feedback to evaluate the growth process and help to assess the performance of corresponding future laser devices in detail.

A cascode gallium nitride (GaN) switch integrating four paralleled GaN depletion-mode metal–insulator–semiconductor–high-electron-mobility transistors (MIS–HEMT) and a silicon MOSFET (Si-MOSFET) is presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the cascode switch. By utilizing an optimized packaging approach, the performance of the multi-GaN-chip cascode switch was evaluated through both static and dynamic characterizations. The constructed cascode switch provides a low-static on-state resistance of 72 mΩ and an off-state blocking capability of 400 V with a positive threshold voltage of 2 V. Analysis of dynamic switching characteristics are discussed and demonstrates stable dynamic on-state resistance (R DS-ON) in inductive load circuits with switching dependencies of voltage, frequency, time, and temperature. The extended defects from buffer caused a minimal decrease in dynamic and static R DS-ON with respect to hard switching conditions. However, there was no noticeable degradation in R DS-ON under harsh switching conditions. This study provides a complete analysis of the multi-GaN-chip cascode switch, including MIS–HEMT manufacturing, cascode packaging and static and dynamic characterizations.

Electron leakage currents seriously limit the power conversion efficiencies (PCEs) of gallium nitride (GaN)-based laser diodes (LDs). To minimize the leakage currents, electron blocking layers are generally applied in the p-type region. However, few works have discussed the electron blocking effect of a p-cladding layer, which is found to be critical in suppressing the leakage currents of an LD. In this work, we compare the blocking performance of uniform AlGaN p-cladding layers and AlGaN/GaN superlattice (SL) p-cladding layers with the same average Al component respectively. Both light-emitting diodes (LEDs) and LDs with the same epitaxy structures are characterized by light–current (L–I) and current–voltage (I–V) measurements. The latest analytical model of leakage currents is applied to fit the L–I curves of LEDs, where smaller leakage coefficients are observed in the SL structures compared with the uniform-layer structures. Eighty LDs with varying ridge widths are studied by comparing the threshold current densities, slope efficiencies, and PCEs. The SL-based p-cladding layer shows statistically significant advantages over a uniform AlGaN layer. The blocking effects of both scattering- and bound-state electrons in SLs are investigated theoretically. Repetitive reflection and thermal relaxation are responsible for the blocking effect of scattering-state electrons. Simulation results indicate that the tunneling effect of bound-state electrons through a miniband mechanism is insignificant at a large injection level due to a negative differential conductivity by the Esaki–Tsu effect. We demonstrate a better electron blocking performance of p-cladding layers based on SLs than uniform AlGaN layers in GaN-based LDs.

The GaN epilayer grown by hydride vapor phase epitaxy was wet etched by phosphoric acid as the etchant. X-ray diffraction confirms that the GaN has a wurtzite structure. Scanning electron microscopy shows various sizes of hexagonal pits for different times of etchant reactions. Atomic force microscopy shows increase in surface roughness with different etchant rate. The photoluminescence gives a 3.4 eV luminescence for the pristine GaN epilayer. In the etched films, the deep-level defect belonging to yellow and green luminescence was found. The deconvoluted Ga 3d peaks of etched samples show Ga-rich epilayers. Micro-Raman spectroscopy is a non-destructive method for measuring carrier concentration, phonon lifetime and strain using A 1 (LO) spectra of Raman vibration mode was utilized via the Lorentz fitting method. The carrier concentration increases while the phonon lifetime decreases with etching rate. Overall, in the 9 min reaction, the epilayer was etched heavily with a perfect hexagonal etch pit structure.