Since high efficiency and low cost have become the leading trend of semiconductor packaging, dual-arms chips mounters have been widely used to eliminate the time delays and improve the efficiency. However, the auxiliary motion is required to avoid spatial interference, which increases the complexity of trajectory. In addition, the motion parameters need to be constantly adjusted online to balance the chips patch efficiency and operation stability, whereas chips placement efficiency needs to online monitor, which is laborious, difficult to adjust the motion parameters rapidly. To offline analyze the packaging efficiency, this article establishes a calculation model for chips patch efficiency of dual-arms mounter, which accurately establish the quantitative relationship between motion parameters and efficiency, narrowing the selection range of motion parameters. First, the process sequence of chips patch is constructed, and the efficiency calculation model is established. Second, considering the characteristics of the time-varying displacement, the method for solving the running time of each process under the flexible velocity control is proposed. Then, the chips patch efficiency is calculated for different parameters, and the effects of the motion parameters and the lead frame structures on chips patch efficiency are investigated, so as to optimize motion parameters, and simulation and calculation results of point to point (PTP) motion are in good agreement with the experimental results, which provide an effective guidance for accurately calculating chips patch efficiency offline and lay a foundation for selecting motion parameters.

All-Cu interconnects with fine pitch scalability and excellent electrical performance are highly considered the next interconnection node for the coming era of chiplet integration. However, current all-Cu interconnection through Cu–Cu direct bonding relies much on expensive chemical mechanical polishing (CMP) processes to reduce surface roughness to several nanometers. Herein, Cu nanoparticle (CNP) film prepared by pulsed laser deposition (PLD) was successfully patterned into micro bumps of $120 \mu \text{m}$ pitch and sintered at 160 °C–250 °C to form all-Cu interconnects without using CMP pretreatment. The fabricated bumps had a low Young’s modulus of only 1 GPa and could produce vertical collapse of several microns in bonding process, providing compliance with surfaces having high roughness and poor coplanarity. The bonded interconnects also exhibited excellent mechanical quality with shear strength $>$ 20 MPa at 160 °C, 15 MPa and $>$ 90 MPa at 250 °C, 20 MPa, which was superior to most reported Cu–Cu bonding using patterned nanomaterials. Patterning mechanism in PLD process involving incident characteristics of CNP flux, evolution of bump morphology was investigated and bump morphology’s influence on bonding properties was analyzed in detail. The strategy illustrated here could lead to develop a low-temperature, low-pressure assembly technique with less reliance on CMP for all-Cu interconnection.

This article presents the synthesis and design of multiband bandpass filters (MBPFs) with inline topology. The coupled-line coupling structures are employed to achieve multichannel responses and a compact footprint. Two different approaches are developed in this research to implement coupled-line MBPFs based on frequency transformation methods. The first synthesis method is based on the direct mapping technique. According to this method, a quad-band bandpass filter (BPF) is theoretically synthesized and designed. The second proposed method is based on generalized ladder-type network analysis with frequency-invariant reactance elements (FIRs). It enables designing MBPFs with an arbitrary number of passbands. To validate this method, a sext-band MBPF is theoretically investigated, synthesized, and designed in microstrip technology as well. Very good in-band filter performance and very good band-to-band isolation are observed for the proposed MBPFs. These results show that the proposed synthesis methods and structures are attractive solutions to design MBPFs with coupled line technology.

In this article, the equivalent thermal circuits of microstrip lines are proposed based on the equivalent spreading angle (ESA) model and convection boundary conditions. Unlike the conventional constant-angle assumption, the ESAs corresponding to the situations of conductor and dielectric losses of microstrip lines are determined precisely by means of the modified parallel-plate model (MPM), which are associated with the geometry and material of the microstrip lines. Furthermore, different kinds of boundary conditions are considered in the thermal circuit models, especially the impact of heat convection condition, which matters in realistic situations. In addition, the thermal circuit models are extended to the case of coupled microstrip lines. The calculated results of the proposed model agree well with those simulated by the multiphysics solver.

Frequent failures in interconnected materials in microelectronic packages play a vital role in determining the reliability of electronic devices. Differences in the thermal expansion coefficients of the solder joint, printed circuit board (PCB), and electronic package are a major source of applied stress on solder joints. Due to health concerns and governmental regulations associated with using leaded solder alloys, SAC solder alloys are commonly used as an alternative to Pb alloys because of their outstanding solderability and reliability [organic solderability preservative (OSP)]. The shear fatigue creep accelerated test at different load levels (16, 20, and 24 MPa) was implemented in this study by using a universal microtesting machine to investigate the solder joint reliability. The creep effects were demonstrated by employing 60 s of dwell time for each alternating stress value and comparing its impact on solder joint reliability with the fatigue test results. The accelerated test was applied to SAC305 (96.5% Sn, 3% Ag, and 0.5% Cu) solder joints with OSP surface finish at different testing temperatures (25 °C, 60 °C, and 100 °C). Seven replicates were considered as a sample size for the reliability analysis. A two-parameter Weibull distribution was employed as the dominant distribution to describe the fatigue behavior at each condition. The characteristic life and shape parameters at each condition were extracted from the obtained Weibull models. The stress–life equation was used to estimate the reliability performance of the solder joints against fluctuations in stress amplitude at different testing temperatures. The inelastic work per cycle and plastic strain were calculated from the acquired hysteresis loop under each condition. Coffin–Manson and Morrow energy models illustrate the relationships between fatigue life versus plastic strain and inelastic work, respectively. The effects of the oscillated testing temperature on the stress–life model, Morrow energy model, and Coffin–Manson model were elaborated using the Arrhenius equation. The results indicated a severe degradation of fatigue life with increased testing temperature. Raising the stress amplitude had a less significant impact on fatigue life reduction than increasing the testing temperature. The reliability prediction models, as a function of the fatigue properties and testing temperature, were derived from the Arrhenius, Coffin–Manson, and Morrow energy models. The acquired prediction equations produced acceptable goodness-of-fit values. Finally, a general reliability model with a 99% adequacy value ( $R^{2}$ ) was constructed as a function of testing temperature and stress amplitude.

This letter reports the quality factor ( $Q$ -factor) of a fused silica planar frame resonator (PFR). The PFR is an axisymmetric structure composed of a beam head, a bridge, two wings, two longitudinal beams, and a supporting tail. Fused silica PFR with a 6 mm beam length is chemically etched from a 500- $\mu \text{m}$ -thick silica glass wafer. The resonant frequency of the flexural mode is measured to be 9654 Hz and the $Q$ -factor as high as 1.13 million is acquired by the ringdown method. The $Q$ -factor of the PFR has the potential for further improvement with structural design and fabrication optimization.

Wireless fully passive neural recording systems are demonstrated with heterogeneous integration of sensing, mixing, and communication components in flexible polymer dielectric films. The recording neurosensor has an antenna, antiparallel diode, and a bypass capacitor to modulate an incoming carrier signal with the neuropotentials and backscatter the mixed signal to an external reader circuit. Planar antennas are realized on liquid crystal polymer (LCP) flexible substrates with low dielectric constant. The designed antenna topology is realized with a single metal layer and eliminates the dependency on substrate thickness, and leads to thinner sensors. This is a major advance compared to prior passive neural recording with rigid and thicker substrates and components. Approximately, 80% thickness reduction and 20% volume reduction are achieved with a similar performance when compared to earlier studies. Our approach thus leads to low-cost and disposable wireless neurosensors on a flexible platform with heterogeneous integration. This article thus advances innovative wireless neural recording in three aspects: 1)advanced packaging for miniaturized neural recording with passive telemetry, through which the overall size of the sensor is reduced without degrading the performance; 2) new antenna topologies for neural recording applications; and 3) detailed power link analysis to estimate the minimum signal sensitivity.

Solder joint inspection (SJI) is a critical process in the production of printed circuit boards (PCBs). Detection of solder errors during SJI is quite challenging as the solder joints have very small sizes and can take various shapes. In this study, we first show that solders have low feature diversity and that the SJI can be carried out as a fine-grained image classification (FGIC) task that focuses on hard-to-distinguish object classes. To improve the fine-grained classification accuracy, penalizing confident model predictions by maximizing entropy was found useful in the literature. In line with this information, we propose using the $\alpha $ -skew Jensen–Shannon divergence ( $\alpha $ -JS) for penalizing the confidence in model predictions. We compare the $\alpha $ -JS regularization with both existing entropy-regularization-based methods and the methods based on the attention mechanism, segmentation techniques, transformer models, and specific loss functions for FGIC tasks. We show that the proposed approach achieves the highest F1-score and competitive accuracy for different models in the fine-grained solder joint classification task. Finally, we visualize the activation maps and show that with entropy regularization, more precise class-discriminative regions are localized, which are also more resilient to noise. The code is available at http://github.com/furkanulger/SJI-entropy-reg .

In recent years, the development of mica paper capacitor (MPC) technology has dramatically improved the withstand voltage and energy storage density of capacitors, which is suitable for pulse power systems. The lifetime of capacitors is a key factor that ensures the reliability of a system. In this article, the investigation of the lifetime characteristics of MPCs under microsecond pulse is presented. The structure of an MPC is analysed, and two numerical simulations are performed to study its characteristics. A lifetime test platform is established to test MPCs, which has stable operation performance. Essential electrical degradation parameters of MPCs are obtained and analyzed. The operational factors that influence the lifetime of MPCs are analysed, and a lifetime empirical model under given operational factors is proposed based on the lifetime test results. The results suggest that the lifetime empirical model could match well with lifetime test results. Furthermore, the structure of a pulse forming network (PFN)-Marx is analyzed by the lifetime model, and constructive suggestions are proposed. This article is devoted to studying the characteristics of MPCs and analyzing the lifetime under various operational factors, which finally helps the device to specify operating conditions and ensure reliability.

The relative motion at the contact interface induced by engine vibration is one of the most significant causes of fretting damage. However, at present, several vibration simulation models have been investigated in literature to predict fretting degradation. Unfortunately, those finite element (FE) models do not take into account all the connector components (more than 10) with the cable, the non-linear mechanical contact, and the prestress state of different components after the assembled process. This article describes and illustrates the approaches used for 3-D FE modeling and vibration simulation of electrical connectors to evaluate the relative displacement between the terminals at contact point, and when the fretting occurs. A series of experimental tests were also conducted to validate the simulation. A sinusoidal vibration with a single frequency and amplitude was applied to the connector system. It was demonstrated that the test and simulation presented similar results. Finally, an approach for predicting the connector risk of fretting damage is established by combining the contact endurance and relative motion at the contact point and eventually quantifying the threshold amplitude of fretting.

This article proposes a scalable substrate-integrated waveguide (SIW) module accommodating an in-line vector modulator monolithic millimeter integrated circuit (MMIC). The SIW module is realized with low-temperature co-fired ceramic (LTCC) technology, and it can be inserted in a dielectric-filled waveguide (DFWG). The module combines $\lambda _{g}/4$ -transformer-based $E$ plane tapering and SIWs on LTCC with the wire-bonded vector modulator. The proposed active LTCC module and two passive test structures (i.e., a constant-height-SIW module and a SIW module with $E$ plane taperings) are manufactured and tested as in-line modules in a DFWG. The passive test structures with the waveguide-to-DFWG and DFWG-to-SIW transitions measure 3.1 and 4.6 dB of insertion loss on average, respectively, at the 71–81 GHz frequency range. The active LTCC module measurements demonstrate a DFWG with phase and amplitude tuning capability and gain up to 17.6 dB within the same frequency range. A four-channel mock-up module with $\lambda _{0}/2$ channel spacing is designed and manufactured to demonstrate the scalability of the design.

In board-level routing, ordered escape routing (OER) becomes a key problem. In this article, given a set of escape pins inside a pin array, a set of available boundaries, and the capacity constraint between two adjacent pins, an efficient algorithm can be proposed to solve the routing problem in OER under capacity constraints. First, based on the mapping process of the detouring paths of the untangled nets in one-sided net untangling, the routability-driven pins of the untangled nets can be assigned onto feasible positions and the target pins of the escape nets can be assigned on some available boundaries. Furthermore, based on the assignment of the routability-driven detouring paths with the capacity consideration, the global wires of the escape nets in a pin array can be assigned in single-layer global routing and the routing paths of the escape nets in a pin array can be assigned in single-layer detailed routing. Compared with Luo’s satisfiability (SAT)-based algorithm, Jiao’s flow-based algorithm, and Yan’s heuristic algorithm for the six tested examples with capacity as 1, our proposed algorithm can obtain the same 100% routability of the escape nets. Compared with Yan’s heuristic algorithm for the other six tested examples with capacity as 2, our proposed algorithm can use reasonable CPU time to improve 1.9% of the total length of the routed escape nets and 0.25% of routability of the routed escape nets on the achievement of the 100% routability on the average.

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal–oxide–semiconductor field-effect transistor (MOSFET). To achieve superior reliability of packaging, we applied the nondominated sorting genetic algorithm with elitist strategy (NSGA-II) and ant colony optimization–backpropagation neural network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermomechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability aging tests on the prepared devices.

Growth of voids driven by electromigration in current carrying metal thin films is a common mode of failure in microelectronic devices. Studies have shown that electromigration-driven void growth rate in such devices is inversely related to the interface adhesion strength between the current carrying metal thin films and the passivation layers on top of the metal films. In this article, we characterize the degradation in electromigration resistance with temperature in metallic thin films with passivation and argue on a general mathematical form for connecting the electromigration resistance to adhesion strength. Test structures with thin-film Cu metal lines are designed and fabricated for performing electromigration experiments and characterizing the void growth rate. Tests are carried out on devices with Cu thin film having TiN and SiNx as passivation layers, over a range of current densities and temperatures. The growth rates of the voids in the Cu lines undergoing electromigration are analyzed using classical models from the literature. The experimental observations on void growth rate with an increase in current density and temperature are validated by comparing the data to those from prior literature. The void growth is also simulated, and the void interface is tracked using an explicit boundary tracking computational technique. It is observed that the contribution of interface adhesion strength to electromigration resistance decreases with an increase in temperature. That is, the experiments suggest that the passivation layers cease to provide resistance to electromigration with increasing temperature. Based on the test results, we develop a general form of a mathematical model to describe the degradation in electromigration resistance with metal film adhesion to the passivation layer.

One of the key requirements for mass production of die-to-wafer Cu bonding is preventing copper surface oxidation. In this study, Cu bonding utilizing an Ag nanolayer was examined to achieve both Cu surface oxidation prevention and low-temperature bonding. The primary focus was to evaluate the impact of the annealing process on the Cu bonding quality. The Cu surface was coated with a 15-nm-thick layer of Ag using an evaporation technique. Cu wafer-to-wafer bonding was performed at a temperature of 180 °C for 30 min, followed by annealing at 200 °C for 60 min. The annealing process resulted in the complete diffusion of Cu into the bonding interface, leading to a uniform and pure Cu-to-Cu bonding. However, the Ag nanolayer did not completely dissolve into the Cu thin film and formed a thin Ag band. The average shear strength of the specimens subjected to the annealing process was $\sim $ 6.5 MPa, which was relatively low. Nonetheless, the annealing process has proven to be a very effective way to create a homogeneous bonding interface and achieve pure Cu–Cu bonding when using Ag nanolayers in Cu bonding.

The shift to lead-free solder alternatives led to the development of Sn–Ag–Cu (SAC) alloys as the most used solders due to their superior mechanical properties and reliability. However, their melting range (217 °C–222 °C) is much higher than that of lead (Pb)-based solders. With advances in microelectronics packaging at aggressive silicon nodes and complex heterogeneous architectures, the high melting temperatures of SAC-based solders significantly affect the package stress, leading to poor joint quality and early interlayer dielectric (ILD) delamination failures. Owing to this, lead-free low-temperature solders (LTSs) have gained momentum with focus on novel alloying compositions. Sn–Bi and In-based solders have emerged as the leading candidates for LTSs. This review article details the key requirements of LTS and evaluates the impact of alloy modifications to the microstructure, thermal/ mechanical properties, wettability, and reliability of Sn–Bi and In-based solder systems. This article also discusses the potential focus areas, especially hybrid LTS, as the bridge between SAC-based to full LTS joints.

Thermocompression ultrasonic flip bonding has been widely used in semiconductor packaging. In order to better understand the mechanism of bonding interface formation of thermocompression ultrasonic flip bonding. A 3-D dynamics finite element model (FEM) of the chip, gold bumps, and substrate was developed, which considers the softening effect of gold bumps during the bonding process. The effects of pressure application position, pressure magnitude, temperature, and ultrasonic power on the stress and plastic strain in the chip, gold bumps, and substrate were analyzed. The results indicated that the maximum stress and plastic strain occurred at gold bumps and the edge of under-bump metallization (UBM) layers for the global model, while the maximum stress at a single bump appeared in the central region. The pressure application position had a minor effect on reducing stress concentration, but had a significant effect on reducing plastic strain concentration. The pressure under various amplitudes had a major effect on the stress, while temperature had a minor effect. The results may provide some references for thermocompression ultrasonic flip bonding of chips.

Packaging of flexible electronics is essential for e-textile applications to reduce degradation of performance caused by mechanical stress and environmental effects and to increase durability. Conformal coatings for packaging have the advantage of reducing rigidity and can be seamlessly integrated into fabrics. Vacuum forming is a technique for packaging electronic devices with thermoplastic films of various thicknesses providing uniform coating. Polyurethane is a widely used thermoplastic material in e-textile and can be easily processed by vacuum forming for packaging. In this article, a detailed explanation of the working of Formech 450DT vacuum former is discussed for packaging small electronic chip for e-textile application with thermoplastic polyurethane (TPU). Two types of flexible circuits were packaged: a carbon monoxide (CO) gas sensor and a series of resistors on flexible PCB. The packaged CO flexible sensor and series resistors endured 5.3 times and 1.7 times, respectively, more bending cycles than unpackaged flexible electronic filament samples. For the washing cycles, the packaged flexible strips with CO sensor and series resistors endured 1.5 times.

The adoption of silicon carbide (SiC) devices in the electric vehicle (EV) industry is increasing due to their superior performance over silicon devices. SiC devices enable further miniaturization of EV inverters, increasing their power density, which results in thermal management challenges. In this article, the limits of single-phase jet impingement cooling are explored for an automotive SiC power module. We propose embedding pin fins in the direct-bonded-copper (DBC) substrate of the power module package using laser powder bed fusion (LPBF) additive manufacturing. The thermal-hydraulic performance of the DBC-embedded pin fins is compared against folded fins that are directly soldered to the DBC substrate. A heat conduction analysis was conducted on an SiC package to determine the target heat transfer coefficient (HTC) for the heat sink. A water–ethylene glycol (WEG) jet impingement on the proposed concepts was studied using unit-cell models to achieve the target HTC. The studied designs put emphasis on the reliability and manufacturability requirements of the automotive industry. The thermal performance of DBC-embedded pin fins outperformed the DBC-soldered folded fins. The performance of the DBC-embedded pin fins is benchmarked against WEG-based cooling systems of commercial EVs. With the proposed cooling solution, we have shown a pathway of reducing the specific thermal resistance by 75% compared to the BMW i3 thermal management system without any penalty on pressure drop or parasitic power.

The conventional design of filters requires numerous simulations, taking a substantial amount of time and computational resources and requiring extensive expertise. This article presents a new method to design filters using an optimization algorithm, which can use the fitness function to evaluate the filters autonomously. Experimental results from designing two common filters, including a microstrip filter and a waveguide filter, demonstrate that the proposed approach produces satisfactory results.