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In this article, the effect of dummy gate bias of a novel In0.53Ga0.47As/InP heterostructure trench-gate pentode power device is investigated by TCAD simulations. The dummy gate relaxes the electric field at the main trench-gate corner and increases the Off-State breakdown voltage ( $\text{V}_{\mathrm {BR}}$ ) of the optimized device for improved reliability. It is shown that the device offers a 27.4% and 16% increase in $\text{V}_{\mathrm {BR}}$ compared with the conventional silicon-based trench-gate device and the In0.53Ga0.47As/InP heterostructure trench-gate device without the dummy gate respectively. We demonstrate that the use of a dummy gate within the high-field, wide bandgap region reduces the Off-State leakage current in InGaAs/InP MOSFET. The proposed pentode device has a lower feedback capacitance and a 91.9% decrease in the gate to drain charge ( $\text{Q}_{\mathrm {GD}}$ ), thus reducing the switching loss. It is thereby improving the static figure of merit (FOM) $V_{\mathrm {BR}}^{2}/\text{R}_{\mathrm {ON}}$ (here $\text{R}_{\mathrm {ON}}$ is the ON-resistance) by $19\times $ and reducing the dynamic FOM $R_{\mathrm {ON}} \times \text{Q}_{\mathrm {GD}}$ by $151\times $ , respectively, for power switching application.

Along with radiation sensing, necessity to study and design reliable radiation hardened devices is also increasing now-a-days. These devices are tolerant to high dosage of radiations without causing any physical damage, logic damage or data loss. In the current work, stacked gate Junctionless FinFET (SG JL FinFET) is analyzed as radiation hardened device by studying the impact of radiation of Linear Energy Transfer (LET) values ranging from 2MeV.cm2/mg to 10MeV.cm2/mg on the device performance. The proposed radiation hardened FinFET is experimentally calibrated with pre and post irradiation data. Single event upset (SEU) study using transient analysis is carried out to study the performance of proposed radiation hardened device at microwave frequency. High-k material-hafnium dioxide is used as gate oxide material to improve radiation hardness of SG JL FinFET. Electrical parameters-drain current, surface potential and SEU generation rate are studied to analyze device characteristics. Optimization of gate oxide, doping concentration, gate metals and temperature is carried out to enhance the reliability of device in terms of radiation hardness. SG JL FinFET is exposed to different types of waves- UV rays, X-ray, and Gamma rays to study the response of device at different frequencies. The comparison of SG JL and SG Inversion Mode (IM) FinFET has been performed. Comparison of SG JL FinFET with previously reported Inverted mode FinFET, L-shaped tunnel FET and Fully Depleted Silicon on Insulator (FD-SOI) MOSFET is carried out to find most suitable device which can provide highest immunity to radiation exposure. Response of JL FinFET based CMOS inverter in presence of radiation is studied and is also compared with other available CMOS inverters.

Field plate technology is an effective method for improving the breakdown performance of AlGaN/GaN high electron mobility transistor (HEMT). Currently, field plate optimization relies on TCAD simulation, which is time-consuming and difficult to converge. In this study, we propose a fast and efficient method to optimize the gate-source dual field plate (dual-FP) to improve the breakdown performance of the HEMT. Specifically, an artificial neural network (ANN) model was used to fit the relationship between the dual-FP structure parameters and the breakdown voltage (BV), so that the breakdown performance could be predicted quickly and the average prediction error was only 3.06%. Furthermore, the trained ANN model was applied to the particle swarm optimization (PSO) algorithm and a dual-FP HEMT with a breakdown voltage of 1228 V was obtained by optimization. The proposed method shows significant advantages in terms of optimization efficiency and can realize automatic optimization. It also provides a reference for the optimization of other field plate structures of microelectronic devices.

Negative bias-temperature instabilities and low-frequency noise are investigated in strained Ge ${p}$ MOS FinFETs with SiO textsubscript 2/HfO textsubscript 2 gate dielectrics. The extracted activation energies for NBTI in Ge ${p}$ MOS FinFETs are smaller than for Si ${p}$ MOSFETs. Low-frequency noise magnitudes at lower temperatures are unaffected by negative-bias-temperature stress (NBTS), but increase significantly for temperatures above $\sim 230$ K. The increased noise due to NBTS is attributed primarily to the activation of oxygen vacancies and hydrogen-related defects in the SiO2 and HfO2 layers.

To analyze the mechanism of the positive bias temperature instability (PBTI) of 4H-SiC MOSFETs based on existing models and predict the practical PBTI lifetime in low stress operation, its possible models were classified by the magnitude of the stress gate voltage $(V_{GS\_{}stress})$ under high-temperature gate-bias (HTGB) stress and channel plane orientations: Si-face (0001), C-face (000-1), and a-face (11-20). The test samples were vertical MOSFETs with planar surface channels on the Si- or C-face and trench-sidewall channels on the a-face. The measurement-stress-measurement cycles that alternately repeat the HTGB stress and the conventional drain current - gate voltage $(I_{D}-V_{GS})$ sweep derived the gate threshold voltage shifts $({\Delta }V_{TH}$ ( $t_{s}, sweep$ )) measured after both the stress time $(t_{s})$ and the $V_{TH}$ -shift-recovery with the sweep process. These were more conspicuous on higher $V_{GS\_{}stress}$ ( $>$ approximately 35, 25, and 30 V for the Si-, C-, and a-faces, respectively) at stress temperature $(T_{stress})\,\,=$ 448 K, identified as components trapped in the gate oxide bulk of the Fowler-Nordheim tunneling electrons. For lower $V_{GS\_{}stress}$ ( $=$ 15 V), we measured ${\Delta }V_{TH} (t_{s}, t_{r})$ as a function of $t_{s}$ followed by the relaxation time $(t_{r})$ at $T_{stress}\,\,=$ 293, 448, and 573 K. ${\Delta }V_{TH} (t_{s}, t_{r})$ was analyzed by the capture/emission time (CET) mapping suitable to evaluate the barrier energy beyond which channel electron carriers are (de-)trapped on the MOS interface states. The CET map successfully illustrated the dependence of ${\Delta }V_{TH} (t_{s}, t_{r})$ on $T_{stress}$ , demonstrating negative or positive correlation owing to shallower or deeper traps, early in the relaxation phase or after long-term $t_{s}$ , respectively. This also enabled to estimate the lifetime for a defined allowable limit of ${\Delta }V_{TH} (t_{s}, t_{r})$ . When the lifetime is set to about 30 years, the reaching ${\Delta }V_{TH}$ ( $t_{s}, sweep$ ) was calculated to be approximately 70, 150, 350 mV for the Si-, C-, and a-faces, respectively, after $t_{s}\,\,=$ 1E9 s $(\approx 30$ years) at $T_{stress}\,\,=$ 448 K on $V_{GS\_{}stress}\,\,=$ 15 V.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

The insulated gate bipolar transformer (IGBT) is widely used in industry, aerospace, renewable energy and other fields, which requires high reliability. However, in the research field of IGBT health evaluation, there are still problems that the accuracy is not high enough and the reliability manager of IGBT cannot accurately grasp. In this study, an IGBT health status evaluation model based on improved krill herd optimized extreme learning machine (IKH-ELM) is proposed to accurately evaluate the health status of IGBT, provide guidance for timely replacement of components, thus reducing the failure probability and maintenance cost, and improving the system reliability. Firstly, the power cycle accelerated aging test, short pulse-high amplitude current test and thermal resistance measurement test are carried out to obtain the failure predictor parameters data of IGBT. Then, an IGBT health status classification method based on cloud model is proposed to make the health status assessment results more scientific. In addition, since the random selection of weights and thresholds of ELM affects the performance of the model, the krill herd algorithm is improved to optimize ELM for obtaining better prediction ability. Based on this, a prediction model based on IKH-ELM is established. Finally, the proposed model is proved to be more accurate and effective under the same experimental environment and the same index.

A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application.

In many applications, power modules are subject to varying operating conditions and critical power cycles which cause the chip temperature to fluctuate. This will reduce the power module reliability due to thermal stresses. It can be beneficial to constrain the temperature variation through thermal management. This article proposes to integrate multiple phase change materials into the power module for such a purpose and verifies the concept by simulation of different operation scenarios. Experiment results on a power module containing two kinds of phase change materials show the superiority in reducing chip temperature at normal and high current conditions. The method can effectively reduce the chip temperature fluctuation of power modules with changing power or current level.

In this paper, the prospect of strained Si/Si0.9Ge0.1 super-lattice nano scale vertically doped $\text{p}^{+}$ -i- $\text{n}^{+}$ (pin) device/switch array has been reported for ultra-fast switching operation in MM-wave frequency regime. The authors have developed a new simulator based on Quantum Corrected Drift-Diffusion (QMCDD) Carrier transport equations for analyzing the switching properties of strained Si/Si0.9Ge0.1 super-lattice structure based SPST, SPDT and SPMT $\text{p}^{+}$ -i- $\text{n}^{+}$ (pin) switches. The enhancements of switching properties are achieved by introducing a small mole fraction of Ge into the Si intrinsic region in the device. The physical and electrical properties of strain induced Si/Si0.9Ge0.1 semiconductor have made this material more attractive for fabrication of high frequency ultra-fast switches in modern communication sectors/industry in a more feasible way. In this research work the out-plane mobility is enhanced by the inclusion of in-plane strain depending on the dimension and the structure of the intrinsic region in the device. The reliability study of the proposed model is also reported in details. According to the authors’ knowledge, this is the first report on Si/Si0.9Ge0.1 super-lattice structure based $\text{p}^{+}$ -i- $\text{n}^{+}$ (pin) switches with strain engineering.

Ring-based, resonant Si photonic (SiPho) devices are temperature sensitive and require thermal tuning for stable operation, which is accomplished with integrated metallic heaters. This paper investigates the combined electromigration (EM) and thermal performance of tungsten (W) heaters using calibrated electro-thermal finite element models. The current injectors that are used to supply the current to the heater are a known weak spot for electromigration. The presented modelling study shows the conflicting design requirements for optimal thermal performance and optimal EM performance, which results in the need of a careful trade-off, supported by experimental reliability data. Based on modelling results, new device designs are proposed with significant performance increase. Lastly, a new methodology is introduced which allows to predict the lifetime of the W-heaters, given specific operating conditions such as ambient temperature and required phase shift.

We report on an atomic-scale study of trap generation in the initial/intermediate stages of time-dependent dielectric breakdown (TDDB) in high-field stressed (100) Si/SiO 2 MOSFETs using two powerful analytical techniques: electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR). We find the dominant EDMR-sensitive traps generated throughout the majority of the TDDB process to be silicon dangling bonds at the (100) Si/SiO 2 interface ( ${ \boldsymbol {P}}_{ \boldsymbol {b} \boldsymbol {0}}$ and ${ \boldsymbol {P}}_{ \boldsymbol {b} \boldsymbol {1}}$ centers) for both the spin-dependent recombination (SDR) and trap-assisted tunneling (SDTAT) processes. We find this generation to be linked to both changes in the calculated interface state densities as well as changes in the NZFMR spectra for recombination events at the interface, indicating a redistribution of mobile magnetic nuclei which we conclude could only be due to the redistribution of hydrogen at the interface. Additionally, we observe the generation of traps known as $\boldsymbol {E}'$ centers in EDMR measurements at lower experimental temperatures via SDR measurements at the interface. Our work strongly suggests the involvement of a rate-limiting step in the tunneling process between the silicon dangling bonds generated at the interface and the ones generated throughout the oxide.

The effects of reverse pulse electrical stress on the electrical and trapping properties of Depletion-Mode (D-Mode) GaN high-electron-mobility transistors (HEMTs) are investigated in this paper. The results of HEMT testing show that the device’s electrical characteristics in the OFF-state are degraded after reverse pulse electrical stress cycling, along with the gate-to-source reverse current and drain-to-source leakage current characteristics. In particular, three traps in the device are identified using the voltage-transient method, and the trapping effects in the HEMT are investigated after 70000 pulses of gate reverse electrical stress are applied. The sources of the traps identified in the study include interface traps near the surface of AlGaN or at the SiN interface (DP1), intrinsic defects such as N antisites in the GaN buffer (DP2), and traps in the gate-drain access region (DP3). Comparison with the transient voltage characteristics of the original device shows that the absolute amplitudes of the traps in the device increase after application of the electrical stress, thus indicating an increment in the trap density. It was found that DP1 remained unchanged before and after stress application, which may be the result of an inadequate surface passivation process. With regard to the other two traps, the electrical stress increases the trap density of DP2 and causes the emergence of DP3 as one new trap. These results may be useful in the design and application of AlGaN/GaN HEMTs. These results may be useful in the design and application of AlGaN/GaN HEMTs.

This work comprehensively investigates the self-heating effects (SHEs) in Tree-FET at 5nm technological nodes. A comparative analysis of Tree-FET with Nanosheet FET (NSFET) shows that the Tree-FET (3-channel+2-bridge) is more or less comparable to the 5-channel NSFET rather than with 3-channel NSFET. An in-depth physics-based study shows that considering only one aspect of increasing ON current is insufficient to judge Tree-FETs for future technological nodes. Targeting these facts, device reliability is demonstrated through numerical simulations showing that Tree-FET outperforms in a self-heating situation, which is a prime concern at a lower technology node. 5-channel NSFET shows $\sim {\textbf {24}}\%$ reduction while Tree-FET ( $\text{H}_{\textbf {IB}}\,\,=$ 25nm) shows only $\sim \textbf {20}\%$ reduction in $I_{\textbf {ON}}$ under self-heating. This is because the bridges create a path to heat removal through electrodes and substrate. The peak temperature difference between channels is $\sim \textbf {23K}$ in Tree-FET, whereas, in the case of other counterparts, it is $\sim \textbf {28K}$ . A comparatively smaller variation in the $\text{V}_{\textbf {T}}$ shift due to the self-heating effect is observed in Tree-FET in order to achieve higher $I_{\textbf {ON}}$ , showing a promising candidate for circuitry that requires a high drive current. A comparative lower gate capacitance implies that Tree-FET may perform well in digital switching applications. Though Tree-FET is not comparable to NSFET for analog applications due to lesser intrinsic gain, it shows a lesser degradation in cut-off frequency $(\sim \textbf {3}\%$ ) compared to 5-channel NSFET under a self-heating environment.

This paper proposes a design-for-testability (DFT) scheme and a test method to improve the detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme considers HtD faults which are undefined state faults (USFs). These states do not always lead to incorrect functionality during the test process resulting in test escapes. The proposed DFT scheme, which can be deployed as a standalone technique, is called USFA-DFT (an undefined state fault-aware design-for-testability technique). In this scheme, the USF detection is achieved through using a weak write before reading the cell. The weak write overwrites defective cells, causing an incorrect read output, without flipping the content of defect-free cells. To avoid test escapes or yield loss (over-testing) caused by process variation (PV) effects, we make use of a post-silicon calibration scheme. Next, to improve the detectability of HtD faults in STT-MRAMs, we suggest a hybrid high coverage test method (called H2C-TM) which enhances the previous method called LCHC-DFT (a low-cost high-coverage design-for-testability technique) by combining it with USFA-DFT. This test method improves the HtD fault detection, by applying the weak write (controlled by USFA-DFT) before the stressed read operation (controlled by LCHC-DFT). This hybrid approach has a negligible area overhead (3.18% for a 1 kbit array). The results for the performance evaluation of the H2C-TM scheme show that for intra-cell and inter-cell defects, on average, the improvements of 14.4% and 11.3% of HtD fault coverage, compared to those of LCHC-DFT, are achieved. Also, for intra-cell and inter-cell defects, the proposed hybrid approach outperforms USFA-DFT by 49.8% and 49.3% respectively. Finally, in the presence of the process variation, the proposed test method guarantees a robust DFT with only a maximum deviation of 10% from the nominal value.

Solar Power is a promising way of electricity generation but it comes with a drawback of low conversion efficiency which is caused by several factors, the most prominent being partial shading. Partial shading leads to mismatch of PV cells, resulting in formation of hot spot. This leads to power dissipation and physical damage to PV cells. Consequently, panel’s credibility is called into question. A bypass diode reduces the amount of power dissipated by a shaded cell, but it doesn’t entirely prevent hot spot formation. Moreover, bypass diode doesn’t bypass every small shade as it has a shaded area threshold at and above which it begins to bypass the shaded module. Whereas, the rise in temperature may also be triggered even by a small shaded area, like the area of falling leaves, which further creates reliability issues. A few hot spot mitigation strategies have been devised; however, it still has room for improvement. This paper presents a modified bypass circuit arrangement for reliability enhancement of PV systems and it is evaluated for a $3\times 1 $ PV string. A comparative analysis with bypass diode is carried out in an experimental study. The efficacy of the proposed methodology is verified based on four performance metrics, namely reverse voltage, power loss under partial shading, the sensitivity of the bypass circuit, and the temperature of the hot spotted module. The proposed technique ensures sensitivity enhancement of the bypass circuit towards shade effect; thus, enhancing the reliability of PV system.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.