In semiconductor manufacturing, black silicon (bSi) has traditionally been considered as a sign of unsuccessful etching. However, after more careful consideration, many of its properties have turned out to be so superior that its integration into devices has become increasingly attractive. In devices where bSi covers the whole wafer surface, such as solar cells, the integration is already rather mature and different bSi fabrication technologies have been studied extensively. Regarding the integration into devices where bSi should cover only small selected areas, existing research focuses on device properties with one specific bSi fabrication method. Here, we fabricate bSi patterns with varying dimensions ranging from millimeters to micrometers using three common bSi fabrication techniques, i.e., plasma etching, metal-assisted chemical etching (MACE) and femtosecond-laser etching, and study the corresponding fabrication characteristics and resulting material properties. Our results show that plasma etching is the most suitable method in the case of $\mu \text{m}$ -scale devices, while MACE reaches surprisingly almost the same performance. Femtosecond-laser has potential due to its maskless nature and capability for hyperdoping, however, in this study its moderate accuracy, large silicon consumption and spreading of the etching damage outside the bSi region leave room for improvement.

This article proposes a deep learning approach for automatic segmentation of low-contrast watermark defects on Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS) surfaces. The task of surface defect detection has been tackled by machine vision or deep learning methods. Traditional machine vision methods require expert domain knowledge for feature extraction, and they are computationally intensive. Deep learning methods based on Convolutional Neural Network (CNN) are extremely fast, but can be affected by illumination variations and perform poorly for low-contrast images. In this study, a U-Net type of encoder-decoder architecture is proposed. The Convolutional operation is substituted with the proposed Cosine-Convolutional operation in the encoder layers of the U-Net model with the objective of minimizing the effects of uneven illumination and highlighting the defect region. To further reduce the computation complexity and improve defect segmentation, an attention-like mechanism is used in the semantic encoder-decoder network. Pixel-wise multiplication is applied in the skip connections between encoder and decoder layers of the U-Net to replace the classical concatenation, thus reducing the parameter count of the model. The proposed methods are computationally fast, with an evaluation time of less than 10-ms for an image of $384\times 256$ pixels on a single low-end GPU. Experimental results show that the proposed Cosine-Convolutional encoder-decoder architectures can effectively and accurately be applied for defect detection and segmentation of watermarks in low-contrast CIS images.

Unit-to-unit variation among the production chambers is a long-lasting challenge for Fault Detection and Classification (FDC) development in the semiconductor industry. Currently, various methods are applied for knowledge transfer among chambers and generalized FDC model development. However, the existing methods cannot give a quantitative or qualitative measure for cross-chamber data transferability evaluation. This research proposes a novel methodology for data transferability evaluation and important sensor screening, which can serve as a data quality evaluation tool for any FDC model. In this research, firstly, Time Series Alignment Kernel (TSAK) is incorporated into Multidomain Discriminant Analysis (MDA) algorithm to achieve sensor-based domain generalization. Then, domain-invariant features are directly extracted for sensor visualization. After that, Fisher’s criterion ratios of the labeled good wafer samples and defective ones are computed based on the domain-invariant features of each sensor to quantitatively estimate how easy it is to transfer knowledge of each sensor among chambers, i.e., data transferability evaluation. Lastly, the proposed method develops a Recursive Feature Elimination (RFE)-based sensor selection algorithm to qualitatively analyze the importance of each sensor channel and identify the critical sensor subset. In this study, validation of the proposed method is based on two open-source datasets from real production lines.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

With the downscaling of semiconductor feature size, single wafer wet etching has shown better within-wafer and wafer-to-wafer uniformity. According to previous research and analysis, liquid film thickness has a close relationship with etch loss, and numerical simulations have been applied to calculate liquid film thickness with fixed nozzle dispensing. This study investigated liquid film thickness with scanning nozzle processing and a modeled aqueous tetramethylammonium hydroxide (TMAH) poly etching method. A modified shallow water equation was used to calculate the liquid film thickness under nozzle scanning conditions. Additionally, the liquid film thickness and liquid velocity were coupled with a chemical reaction kinetic model to calculate the TMAH poly etching reaction rate on the wafer surface. Scan dispensing etch loss was calculated by integrating the reaction rate. Both the experimental and simulation results showed that the scan speed can affect within-wafer etch loss profile and that a fast scan speed could increase etch loss in wafer donut area. The simulation model could be a predictive tool for improving within-wafer etching profile.

In current semiconductor manufacturing, limited raw trace data pertaining to defective wafers make fault detection (FD) assignments extremely difficult due to the data imbalance in wafer classification. To mitigate, this paper proposes using a variational autoencoder (VAE) as a data augmentation strategy for resolving data imbalance of temporal raw trace data. A VAE with few defective samples is first trained. By means of extracting the latent variables that characterize the distribution of the defective samples, we make use of the statistical randomness of the latent variables to generate synthesized defective samples via the decoder scheme in the trained VAE. Two data representations and VAE modeling strategies, concatenation of multiple and individual raw trace data as the input of the VAE during the training stage, are investigated. A real-data plasma enhanced chemical vapor deposition (PECVD) process having only few defective samples is used to illustrate the performance enhancement to wafer classification arising from the proposed data augmentation framework. Based on the computational comparisons between noted classification models, the proposed generative VAE model via the individual strategy enables the adaptive boosting (AdaBoost) classifier to achieve perfect performances in every metrics if the 80% and 100% over-sampling ratios are adopted.

The reason for the change of trench sidewall profile under low pressure of SF6/O2 containing plasma was explored by studying the trench morphology under different etching conditions. The result shows that the Si undercut decreases with the decreasing of pressure and the uniformity will become better. However, the sidewall of the trench presents a negatively tapered under low pressure. The reasons for different profile of trench are explored by the thickness of sidewall protective layer for the first time. The TEM results show that the trench sidewall forms a protective film with a thickness of about 100Å. The thickness of the oxide layer decreases from top to bottom. And the EDX results show that the main elements of the protective film are Si and O. Due to the decrease of oxide thickness, the width of trench bottom will become larger and larger, resulting in negatively tapered morphology. It is worth noting that the profile of trench changes to positively tapered again under the condition of low ratio of SF6/O2. Based on this, an optimized trench etching process is proposed and the etch rate is $1.15{\mu }\text{m}$ /min and the selectivity to the oxide mask is 14.

Semiconductor fabrication involves hundreds of process steps through various manufacturing tools. These processing steps are composed of many manufacturing and inspection steps. Inspection is an important step in the fabrication process to determine whether a process is in or out of control. Abrupt manufacturing or inspection tool excursion can lead to a serious low yield problem. Although commonality analysis is a proven tool for detecting abrupt tool excursion, it has gained only limited success in detecting manufacturing tool excursion outside of inspection tools. Compared with manufacturing tools, only a small number of lots or wafers pass through inspection tools. Therefore, it is difficult to construct a sufficient lot history log for inspection commonality analysis in contrast to that of manufacturing tools. Furthermore, inspection may stress a wafer during its own processing, therefore, the target wafer is changed sequentially or randomly. Accordingly, a lot history is apt to include missing traces, which hinders finding inspection tool excursion effectively. In this paper, we propose a comparative analysis framework for commonality analysis algorithms. Performance measures are suggested. To compare the performance of the algorithms effectively, we use a synthetically generated dataset in a simulation experiment. In addition, we apply the algorithms to a real problem that occurred in the fabrication process. Our proposed algorithm demonstrates superiority over the other commonality analysis algorithms in the experiments.

Optimal cyclic scheduling problems of wafer-residency-time-constrained dual-arm cluster tools in wafer fabrication are challenging and remain to be fully solved. Existing studies assume that all processing modules (PMs) of a required type are used to process the same type of wafers. This sometimes brings unneeded conservativeness to scheduling results, because we may be able to make a tool schedulable by reducing the number of PMs in some steps if the original one is not. In some cases, we may use fewer PMs to reach the same result if the original one is schedulable, thus saving energy and other production resources. This work selects a proper number of PMs of needed types to process wafers while ensuring the highest productivity of a wafer-residency-time-constrained dual-arm cluster tool. It proposes the necessary and sufficient conditions under which a tool is schedulable. It then develops a polynomial-complexity algorithm that finds an optimal cyclic schedule. Examples are given to show its superiority over existing ones, thus advancing this field of cluster tool scheduling greatly and helping semiconductor producers to realize the green manufacturing of wafers.

Semiconductor vertical furnaces must achieve even faster and more precise temperature control due to the demand for ever-reducing the minimum feature size or critical dimension in semiconductor chips. Also, the insulation performance of vertical furnaces has improved to reduce power consumption; as a side effect, temperature reduction operation takes longer without active cooling. Therefore, in addition to heaters, vertical furnaces equipped with coolers have emerged to achieve higher productivity, more precise temperature control, and lower power consumption. However, the inability to generate positive and negative control inputs for one of the heaters or coolers poses a challenge for an intuitive controller parameter design. The aim of this paper is to address these issues by proposing an intuitive method for designing a controller in the frequency domain which virtually integrates heaters and coolers. We implemented the controller in a full-scale actual semiconductor vertical furnace and first confirmed that the linearity is high. Furthermore, we experimentally verified that the controller achieves both high-speed, high-precision temperature control and low power consumption.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

As the semiconductor manufacturing process is moving towards the 3 nm node, there is a crucial need to reduce the edge placement error (EPE) to ensure proper functioning of the integrated circuit (IC) devices. EPE is the most important metric that quantify the fidelity of fabricated patterns in multi-patterning processes, and it is the combination of overlay errors and critical dimension (CD) errors. Recent advances in machine learning have enabled many new possibilities to improve the performance and efficiency of EPE optimization techniques. In this paper, we conducted a survey of recent research work that applied machine learning/ deep learning techniques for the purposes of enhancing virtual overlay metrology, reducing overlay error, and improving mask optimization methods for EPE reduction. Thorough discussions about the objectives, datasets, input features, models, key findings, and limitations are provided. In general, the results of the review work show a great potential of machine learning techniques in aiding the improvement of EPE in the field of semiconductor manufacturing.

The requirements on data-driven Machine Learning models for industrial applications are often stricter, compared to those used for academic purposes, as model reliability is critical in industrial environments. Herein is introduced a framework which enables automated data generation with the goal of efficiently providing a data set sufficient to build a reliable and actionable model. Essential to this framework is the placement of the model training/testing data points, which need to be well distributed across the defined input parameter space. The framework is applied to semiconductor fabrication, wherein TCAD, a set of simulation tools that reproduce the physical processing and the final electrical performance of semiconductor devices, is a well-established capability. Transistor-level processing data is reproduced with TCAD simulations, from which the Machine Learning model is built. The framework described here assures that the resulting Machine Learning model fulfills the accuracy requirements across the parameter space. As an example application, the final Machine Learning model is then used to modify the process for a transistor, to obtain both better electrical performance and reduced variability.

Defect detection is a crucial but challenging task in thin film transistor liquid crystal display (TFT-LCD) manufacturing. Existing vision-based methods focus on either spatial domain or frequency domain with unsatisfactory detection. In view of that, this paper proposes a hybrid template matching method by drawing benefits from both frequency and spatial domain techniques. Under proposal, frequency domain template matching method and saliency detector method are firstly adopted separately to obtain two candidate frequency components associated with defects. In template matching process, a novel selection criterion is taken to improve identifying components associated with local spatial anomaly. Subsequently, the inverse Fourier transform is applied on the intersection of the two candidates to reconstruct the defect regions. In final steps, image entropy in the spatial domain is employed to filter out false detection regions to improve accuracy. To meet industry’s real-time inspection requirement, image partition and multi-threading calculation techniques are introduced into the proposed methodology. Experimental results have shown practical viability of the proposed approach to increase the yield rate of panels through robust defect detection in TFT-LCD manufacturing.

In this study, iron oxide (Fe2O3)/graphitic carbon nitride (g-C3N4)/titanium dioxide (TiO2) nanofibers (NFs) were used as an additional layer on photoanode in dye-sensitized solar cells (DSSCs) to improve the photovoltaic performance of DSSCs. The nanofibers were prepared by electrospinning with double jets. The heterogeneous nanofiber composite mainly includes Fe2O3, g-C3N4, and TiO2. The Fe2O3/g-C3N4/TiO2 NFs were characterized by X-ray diffractometer (XRD), and the surface morphology was observed by a field emission scanning electron microscope (Fe-SEM). The electrochemical impedance spectroscopy (EIS) was applied to analyze the impedance of the cell. The incident photon current efficiency (IPCE) measurements were applied to determine the quantum efficiency, and ultraviolet-visible (UV-Vis) spectrophotometer was applied to observe the dye adsorption and absorption wavelength. To understand the performance of the modified photoanodes in DSSCs, we analyzed the photovoltaic parameters. The results suggest that the addition of Fe2O3/g-C3N4/TiO2 NFs is able to improve the conversion efficiency of the modified DSSCs to 4.81%. In addition, the efficiency under different illumination was also analyzed, and the highest conversion efficiency was 6.81% at 30 mW/cm2.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

To satisfy the increasing requirements for high-quality cavity mirrors for semiconductor lasers, the influence of the anisotropic stress field generated by scratching GaAs on the quality of cleavage planes was investigated. First, a novel method for calculating the interplanar spacing was proposed to estimate the favourable direction for the scratching operation. Some mechanical properties in the scratching direction were calculated. Consequently, an anisotropic calculation model of the stress field generated by scratching was established. The calculation model was used to analyse the y-component stress field distribution along different directions beneath the indenter. The results show that the maximum stress occurs at the contact area between the material and indenter tip, and the stress along the orientation is lower than that along the orientation. According to our experiments, a significant decrease in the average radial crack length and a slight decrease in the average kerf width were observed along the [011] direction compared to the corresponding results for the [001] direction. In addition, the (011) plane had a surface roughness of 0.43 nm and could become a preferential cleavage plane under a low scratching load. The results of this study contribute to advance our understanding of the mechanisms of mechanical cleavage processes.

Surface defect detection plays an important role in manufacturing and has aroused widespread interests. However, it is challenging as defects are highly similar to non-defects. To address this issue, this paper proposes a Region of Interest Attention (RoIA) network based on deep learning for automatically identifying surface defects. It consists of three parts: multi-level feature preservation (MFP) module, region proposal attention (RPA) module, and skip dense connection detection (SDCD) ones, where MFP is designed to differentiate defect features and texture information by feature reserved block, RPA is developed to locate the position of the defects by capturing global and local context information, and SDCD is proposed to better predict defect categories by propagating the fine-grained details from low-level feature map to high-level one. Experimental results conducted on three public datasets (e.g., NEU-DET, DAGM and Magnetic-Tile) demonstrate that the proposed method can significantly improve the detection performance than state-of-the-art ones and achieve an average defect detection accuracy of 99.49%.

Exponentially weighted moving average (EWMA) controllers have been extensively studied for run-to-run (RtR) control in semiconductor manufacturing processes. However, the EWMA controller with a fixed weight struggles to achieve excellent performance under unknown stochastic disturbances. To improve the performance of EMWA via online parameter tuning, an intelligent strategy using deep reinforcement learning (DRL) technique is developed in this work. To begin with, the weight adjusting problem is established as a Markov decision process. Meanwhile, simple state space, action space and reward function are designed. Then, the classical deep deterministic policy gradient (DDPG) algorithm is utilized to adjust the weight online. Moreover, a quantile regression-based DDPG (QR-DDPG) algorithm is further verified the effectiveness of the proposed method. Finally, the developed scheme is implemented on a deep reactive ion etching process. Comparisons are conducted to show the superiority of the presented approach in terms of disturbance rejection and target tracking.

High-quality and fast crack segmentation in solar cell electroluminescence images with heterogeneously textured background disturbance is challenging. We propose an end-to-end Efficient and Refined Deep Convolutional Features Network (ERDCF-Net) for precise and efficient crack segmentation. Firstly, we design a lightweight, efficient deep convolutional features (EDCF) encoder by adopting multilevel deep convolutional features to generate a discriminative feature representation of cracks. Moreover, some complicated background disturbance is restrained by reusing rich crack and background features. Secondly, we present a refined side output (RS) decoder by automatically refining side outputs from the EDCF encoder. The experiments demonstrate that the proposed network excellently performs on the solar cell cracks (MIoU of 92.82%, F - measure of 93.58%, and 89 FPS) and open crack datasets (MIoU of 85.6%, F - measure of 84.1%, and 90 FPS).